Physical Design Engineer (Armenia)

Meet the Team Step into Cisco's ASIC Physical Design Team, where innovation meets collaboration. As a group of highly skilled engineers, we’re redefining what's possible in silicon technology. Our mission is to drive the future of chip design, managing full chip physical implementation from RTL to GDSII and beyond. Working hand‑in‑hand with Front‑End teams, we transform cutting‑edge designs into industry‑leading silicon solutions. Here, you’ll have the opportunity to shape tomorrow’s technology, driving advancements in power, performance, and reliability with every project. Together, we’re building the foundation for the future of connectivity. Your Impact In this role, you’ll drive Cisco’s silicon innovation by creating breakthrough solutions that blend hardware and software. You’ll solve complex challenges, accelerate design processes, and deliver impactful technology. Beyond your technical work, you’ll be part of a culture that values mentorship, celebrates success, and supports your growth. This is your opportunity to shape technology that connects and empowers people worldwide. Responsibilities
- You will be responsible for macro level RTL to GDS implementation and signoff.
- Work with Front‑End teams to understand the design architecture to ensure optimal physical implementation.
- Execute physical design tasks, including gate‑level netlist synthesis, floorplanning, placement, Clock Tree Synthesis (CTS), and routing.
- Optimize designs to achieve industry‑leading power, performance, and area (PPA) metrics while maintaining design integrity through formal verification.
- Conduct Static Timing Analysis (STA), physical verification, formal verification and signoff closure to ensure high‑quality results.
- Analyze and resolve Electromigration (EM) and IR‑drop (IR) issues, meeting stringent signoff requirements for reliability and performance.

Minimum Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.
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