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Asic Physical Design Technical Leader (Armenia)

Asic Physical Design Technical Leader (Armenia)
Descripción
This is a hybrid role with four days per week at Cisco’s Yerevan office. Meet the Team Join a world-class Physical Design team at the forefront of advanced SoC development. Our team is responsible for delivering ground breaking silicon solutions that power innovative products across general markets. With a diverse group of highly skilled engineers, we foster collaboration and technical excellence in a fast-paced, supportive environment. The team’s work is integral to achieving high-performance, power-efficient designs that enable next-generation technologies. You'll be part of a vibrant, ambitious group passionate about solving complex challenges and driving industry innovation. Your Impact Drive macro-level RTL-to-GDSII physical implementation and signoff for complex SoCs or large subsystem designs, ensuring high-quality results. Provide technical leadership for architecture-aware implementation strategies by collaborating closely with Front-End, RTL, and system teams. Implement end-to-end physical design processes—including synthesis, floorplanning, placement, Clock Tree Synthesis (CTS), routing, and signoff convergence—to achieve robust and predictable outcomes. Define and drive PPA (power, performance, area) optimization strategies, ensuring design correctness and reliability. Lead STA, physical and formal verification, EM/IR analysis, and signoff closure to meet advanced-node reliability and power integrity requirements. Mentor junior engineers, establish best practices, and partner with CAD, methodology, and EDA vendors to improve flows and enable new technologies. Your contributions will directly impact the success of major tapeouts and the adoption of industry-leading innovations. Minimum Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.
- 10+ years experience in ASIC physical design and implementation.
- Proven track record leading physical design preferably for complex SoCs or large IPs through s Postúlate en Kit Empleo: kitempleo.com.co/empleo/1abseu
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